Szymon Kałużyński
Programista Specjalista
Gdańsk,Pomorskie
Summary
Experienced FPGA programmer with 13 years of experience in VHDL language and work with measurement instruments. Feels confident both in teamwork and in individual tasks. Motivated to gain and learn new experience.
Overview
1
1
Language
6
6
years of post-secondary education
13
13
years of professional experience
Work History
Specialist Programmer
Radmor S. A.
Gdynia
07.2008 - Current
- Developed VHDL model of digital up/down converter in several versions
- Created simulation model of digital up/down converter in Python
- Developed VHDL model of Ethernet MAC GMII module
- Developed VHDL model of control module of radio station
- Participated in creating company's coding rules for VHDL
Graduate Trainee
Radmor S.A., Gdańsk University of Technology
Gdańsk
02.2008 - 05.2008
- Developed and implemented VHDL model of digital up/down converter.
- Created simulation model of DUC/DDC in Matlab.
Education
Master of Science - Microelectronics
Gdańsk University Of Technology
Gdańsk 10.2001 - 12.2007
Skills
Creating RTL models of digital systems with VHDL
undefinedTimeline
Specialist Programmer
Radmor S. A.
07.2008 - Current
Graduate Trainee
Radmor S.A., Gdańsk University of Technology
02.2008 - 05.2008
Master of Science - Microelectronics
Gdańsk University Of Technology
10.2001 - 12.2007
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